Samantak Gangopadhyay received his B.Tech and M.Tech degrees in Electronics and Electrical Communication Engineering (specialization in Microelectronics and VLSI design) from the Indian Institute of Technology, Kharagpur in May, 2009. After graduation, he joined IBM India as a Physical design R&D Engineer and worked on POWER series & Z-Mainframe microprocessors. In this role, he was responsible for the implementation of synthesizable blocks of his units and ensuring that the timing, noise, power, Electromigration, DFT & DFM specifications are met. In Fall 2013, he started his doctoral studies at the Georgia Institute of Technology and joined the Integrated Circuits and Systems Research Laboratory (ICSRL). His research interests include the designing of low power digital circuits, low-dropout voltage regulators, and power management for wide dynamic range computation.
Saad Bin Nasir is currently pursuing his graduate studies in the School of Electrical and Computer Engineering at Georgia Institute of Technology. He joined ICSRL in the summer of 2013. Before coming to Georgia Tech, he received extensive industrial experience as a design engineer at Center for Advanced Research in Engineering (CARE), Pakistan where he was the team lead for physical layer design of wideband software defined radio waveform. He received his B.Engg in Electrical Engineering, with honors, from the National University of Sciences and Technology (NUST), Pakistan in 2010. At Tech, he is investigating the design and development of adaptive power management in nanoscale integrated circuits. His wider research interests include analog, digital and mixed signal IC design and applied control theory.
Abhinav Parihar received his B.Tech. degree from the Indian Institute of Technology Delhi in May, 2012. After one year as a Research Assistant at IIT Delhi, he joined Georgia Tech in Fall 2013 for his PhD in ECE. His research interests include non-linear dynamical systems like coupled oscillators and their applications in computing.
Anvesha Amravati received M.Tech in Microelectronics and VLSI from Indian Institute of Technology-Bombay in 2012. He worked on PVT tolerant analog and bio-medical circuits during his M.Tech. He has authored/co-authored 10 international Conference/Journal publications. He has won first prizes in national design contests organized by Analog Devices and Cadence in India. He was with Rambus chip technologies as a mixed signal design engineer from 2012 to 2014 working on multiprotocol DDR memory interface circuits. In Fall 2014, he has started his graduate studies at Georgia Institute of Technology and started working in ICSRL. His area of interest is in the area of mixed signal circuits and systems.
Insik Yoon received his B.S. & M.S. degrees in Electrical & Computer Engineering from Carnegie Mellon University in May 2010. After graduation, he spent five years in TLi & SK hynix as a digital circuit engineer in high speed link design.In fall 2015, he started his doctoral studies at the Georgia Institute of Technology and joined Integrated Circuits and Systems Research Laboratory(ICSRL).His research interests include STT-MRAM memory system & power management for IoT devices.
Ningyuan Cao received his B.S in program of Electric Power Engineering from Shanghai Jiaotong University, China in July, 2013 and M.S in Electrical Engineering Department (specialization in Analog Circuit Design) from Columbia University in Feb, 2015. After graduation, he worked as a part-time staff-associate of CISL (Columbia Integrated Systems Lab) on project of Adaptive Sampling Model Development and research on Analog Computer applications. In this role, he was responsible for building, testing and evaluating adaptive sampling system model and exploring potential applications for the analog computing chip designed previously in various fields. In fall 2015, he started his doctoral studies at the Georgia Institute of Technology and joined the Integrated Circuits and Systems Research Laboratory (ICSRL). His research interest is mainly on exploration of dynamical hardware systems to solve hard algorithms, including Integer Linear Programming (ILP), graph traversal, image recognition, template matching and etc.