Technology: 180nmA 24V / 48V to 0.8V – 1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon BCD Controller IC (Under Review)
Technology: TSMC 40nmTernary-weight Compute- in-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation (CICC 2021, Best Paper Award)
Technology: 28nmA 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell for Cryogenic Applications (CICC 2021)
Technology: 40nm
Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification (ISSCC 2021)
Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification (ISSCC 2021)
Technology: 65nm
NeuroSLAM: A Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics (JSSC 2021, ISSCC 2020)
NeuroSLAM: A Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics (JSSC 2021, ISSCC 2020)
Technology: 65nm
Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-off (VLSI 2020)
Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-off (VLSI 2020)
Technology: 65nmOPTIMO: Programmable Spatial-Array Processor for Solving Distributed Optimizations (JSSC 2020, ISSCC 2019)
Technology: 65nmEM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation (ISSCC 2020)
Technology: 55nmA Homomorphic Encryption Crypto-Engine for IoT Nodes to Enable Secure Computation on Encrypted Data (CICC 2019)
Technology: 65nmHybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics (JSSC 2019, ISSCC 2019)
Technology: 7nmA Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction (VLSI 2019)
Technology: 130nmSwitched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits (JSSC 2018, ESSCIRC 2016)
Technology: 55nmA Mixed-Signal Neuromorphic Accelerator with Stochastic Synapses and Embedded Reinforcement Learning for Autonomous Micro-Robots (ISSCC 2018)
Technology: 130nmDigitally-Assisted Leakage Current Supply Circuit for Reducing the Analog LDO Minimum Dropout Voltage (CICC 2017)
Technology: 130nmSensor Front-end with in-situ mixed-signal classifier
Technology: 130nmUnified Voltage and Frequency Regulation (ESSCIRC 2016)
Phoenix-II Technology: IBM 130nm
Distributed Digital LDOs with Cross-domain Noise Cancellation (ISCAS 2016, Trans of Power Electronics 2016)
Phoenix-I Technology: IBM 130nm
A Fully Digital LDO with Adaptive Control and Reduced Dynamic Stability (ISSCC 2015, Trans of Power Electronics 2016)
Technology: Intel 32nm
A 2.3nJ/Frame Voice Activity Detector for Context-Aware Systems in 32nmCMOS (CICC 2012, JSSC 2013)
Technology: Intel 22nm
Graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep (ISSCC 2014)
Technology: Intel 32nm
A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance (ISSCC 2010, JSSC 2011)
Technology: Intel 32nm
1.05V 1.6mW, 0.45oC 3σ Resolution ΣΔ based Temperature Sensor with Parasitic Resistance Compensation in 32nm Digital CMOS Process (ISSCC 2009, JSSCC 2010)
Technology: Intel 32nm
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays (JSSC 2011, VLSI 2010)
Technology: Intel 32nm
PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction (ISSCC 2010)
Technology: IBM 130nm
An 85mV 40nW Process-Tolerant Subthreshold 8X8 FIR Filter (VLSI 2007)
Technology: Lincoln Labs 90nm 3D Process
8b 8Tap FIR Filter for Near-Threshold Voltage Operation in 90nm Technology
Technology: TI 130nm
0.13μm CMOS four-channel ADSL2+ analog front-end for CO applications with 75mW per channel (ISSCC 2004)