1. A. Parihar, N. Shukla, S. Datta, and A. Raychowdhury, “Synchronization of pairwise-coupled, identical, relaxation oscillators based on metal-insulator phase transition devices: A Model Study” in Journal of Applied Physics, vol. 117, 054902 (2015)
2. A. Parihar, N. Shukla, S. Datta, and A. Raychowdhury. Exploiting synchronization properties of correlated electron devices in a non-boolean computing fabric for template matching. IEEE Journal on Emerging and Selected Topics in Circuits and Systems,, PP(99):1–10, 2014.
3. Abhinav Parihar, Nikhil Shukla, Suman Datta, and Arijit Raychowdhury. Synchronization of pairwise-coupled, identical, relaxation oscillators based on metal-insulator phase transition devices: A model study. arXiv preprint arXiv:1408.2582, 2014.
4. Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, and Arijit Raychowdhury. A 32nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits. Journal of Solid State Circuits, 11, 2014.
5. Nikhil Shukla, Parihar, Abhinav, Eugene Freeman, Hanjong Paik, Greg Stone, Vijaykrishnan Narayanan, Haidan Wen, Zhonghou Cai, Venkatraman Gopalan, Roman Engel-Herbert, et al. Synchronized charge oscillations in correlated electron systems. Nature Scientific reports, 4, 2014.
6. Helia Naeimi, Charles Augustine, Arijit Raychowdhury, Shih-Lien Lu, and James Tschanz. Sttram scaling and retention failure. Intel Technology Journal, 17(1):54, 2013.
7. A Raychowdhury, C. Tokunaga, W. Beltman, M. Deisher, J.W. Tschanz, and V. De. A 2.3 nJ/frame voice activity detector-based audio front-end for context-aware system-on- chip applications in 32-nm cmos. IEEE Journal of Solid-State Circuits, 48(8):1963–1969, Aug 2013.
8. Arijit Raychowdhury, Bibiche Geuskens, Keith Bowman, James Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad Khellah, Vivek De, “Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays,” Journal of Solid State Circuits (JSSCC), Vol-46, Issue 4, April 2011
9. C. Augustine, A. Raychowdhury, D. Somasekhar, K. Roy, V. De, “Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances,” Transactions on Electron Devices, Vol. 58, Issue 12, Dec 2011.
10. Keith A Bowman, Carlos Tokunaga, James W Tschanz, Arijit Raychowdhury, Muhammad M Khellah, Bibiche M Geuskens, Shih-Lien Lu, Paolo A Aseron, Tanay Karnik, and Vivek K De. All-digital circuit-level dynamic variation monitor for silicon debug and adaptive clock control. Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(9):2017–2025, 2011
11.Keith A. Bowman, James W. Tschanz, Shih-Lien L. Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris B. Wilkerson, Tanay Karnik, and Vivek K. De, “A 45nm Resilient Microprocessor Core for Dynamic Variation Tolerance,” Journal of Solid State Circuits (JSSCC), Dec 2010
12.Sumeet Kumar Gupta, Arijit Raychowdhury and K. Roy, “Digital Computation in Sub-Threshold Region for Ultra-Low Power Operation: A Device-Circuit-System Co-Design Perspective,” Proceedings of IEEE, Vol. 98, Issue 2, 2010
13.Sumeet Kumar Gupta, Arijit Raychowdhury and K. Roy, “Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy” Journal of Applied Physics, Vol. 105, Issue 9, 2009.
14.Bowman, K.A.; Tokunaga, C.; Tschanz, J.W.; Raychowdhury, A.; Khellah, M.M.; Geuskens, B.M.; Lu, S.-L.L.; Aseron, P.A.; Karnik, T.; De, V.K.; , “All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control,” Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.58, no.9, pp.2017-2025, Sept. 2011
15.Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath, “A 1.05V 1.6mW, 0.45oC 3σ Resolution ΣΔ based Temperature Sensor with Parasitic Resistance Compensation in 32nm Digital CMOS Process,” Journal of Solid State Circuits (JSSCC), Vol 44, Issue 12, 2009, pp: 3621-3630.
16.Arijit Raychowdhury, Shekhar Borkar, Vivek De, Ali Keshavarzi and K. Roy, “Variation Tolerance in a Multi-channel Carbon Nanotube Transistor for High Speed Digital Circuits,” IEEE Transactions on Electron Devices (TED), Vol 56, Issue 3, March 2009, pp: 383-392.
17.A. Coker, V. Taylor, D. Bhaduri, S. Sukla, A. Raychowdhury, K. Roy, ”Multi-junction Fault Tolerance Architecture for Nanoscaled Crossbar memory,” IEEE Transactions on Nanotechnology (TNANO), Vol. 7, Issue 2, March 2008, pp: 202-208.
18.Arijit Raychowdhury, Bipul Paul, Swarup Bhunia, and Kaushik Roy, “Computing with Subthreshold Leakage: Device/Circuit/Architecture Co-design for Ultralow-Power Subthreshold Operation”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 13, Issue 11, November 2005, pp: 1213-1224.
19.Myeong-Eun Hwang, Arijit Raychowdhury, and Kaushik Roy, “Energy Recovery Techniques to Reduce On-chip Power Density in Molecular Nano-Technologies”, IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 52, no. 8, August 2005, pp: 1580-1589.
20.N. Banerjee, A. Raychowdhury, K. Roy, S. Bhunia, and H. Mahmoodi, “Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis” , IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 14, Issue 9, September 2006, pp: 1034-1039.
21.Arijit Raychowdhury, and Kaushik Roy, “Carbon Nanotube Electronics: Design of High Performance and Low Power Digital Circuits”, IEEE Transactions on Circuits and Systems I, Vol. 54, Issue 11, Nov 2007, pp 2391-2401.
22.Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Vivek De, and Kaushik Roy, “Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic – Modeling and DC Simulations”, IEEE Transactions on Electron Devices (TED), Vol. 53, Issue 11, November 2006, pp: 2711-2717.
23.Ali Keshavarzi, Arijit Raychowdhury, Juanita Kurtin, Kaushik Roy, and Vivek De, “Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic – Transient Analysis, Parasitics and Scalability”, IEEE Transactions on Electron Devices (TED), Vol. 53, Issue 11, November 2006, pp: 2718-2726.
24.Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, “A Novel Delay Fault Testing Methodology Using Low-Overhead Built-in Delay Sensor”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol 25, Issue 12, Dec 2006, pp: 2934-2943.
25.Arijit Raychowdhury and Kaushik Roy, “Modeling of Metallic Carbon Nanotube Interconnects for Circuit Simulations and a Comparison with Cu Interconnects for Scaled Technologies”, IEEE Transactions on Computer Aided Design (TCAD), Vol. 25, Issue 1, January 2006, pp: 58-65.
26.Arijit Raychowdhury and Kaushik Roy, “Carbon nanotube based voltage-mode multiple-valued logic design,” IEEE Transactions on Nanotechnology (TNANO), Vol. 4, Issue 2, March 2005, pp: 168 – 179.
27.Saibal Mukhopadhyay, Arijit Raychowdhury and Kaushik Roy, “Accurate Estimation of Total Leakage in Nanometer Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile,” IEEE Transactions on Computer Aided Design (TCAD), Vol. 24, Issue 3, March 2005, pp: 363- 381.
28.Arijit Raychowdhury, Saibal Mukhopadhyay and Kaushik Roy, “A Circuit Compatible Model of Ballistic Carbon Nanotube Field Effect Transistors”, IEEE Transactions on Computer Aided Design (TCAD), Vol. 23, no. 10, October 2004, pp: 1411-1420. (Most downloaded paper of 2004)
29.B. C. Paul, A. Raychowdhury, and K. Roy, “Device Optimization for Digital Subthreshold Operation,” IEEE Transactions on Electron Devices (TED), Vol. 52, Issue 2, February 2005 pp: 237- 247.
30.Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, “Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current,” Journal of Electronic Testing: Theory and Applications, March, 2005.
31.Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current,” Journal of Electronic Testing: Theory and Applications, Vol. 21, Issue 2, April 2005.