ICSRL

Integrated Circuits & Systems Research Lab

Publications

 Book Chapters

  1. Bipul Paul and Arijit Raychowdhury, “Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges,” in “Low-Power Variation-Tolerant Design in Nanometer Silicon”, Springer Publications, USA, October 2010.

  2. Ali Keshavarzi and Arijit Raychowdhury, “Carbon nanotubes for digital circuits: Promises, Challenges and Outlook” in “Carbon Nanotube Electronics (Series on Integrated Circuits and Systems)”, ISBN-10: 0387368337 August 2008.

  3. Arijit Raychowdhury and Kaushik Roy, “Nanometer Scale Technologies: Device Considerations” in “Nano, Quantum and Molecular Computing: Implications To High Level Design And Validation”, Kluwer Academic Publishers, ISBN: 1402080670, June 2004.

  4. Amit Agarwal, Saibal Mukhopadhyay, Chris H. Kim, Arijit Raychowdhury and Kaushik Roy, “Power Estimation and Reduction” in “System on Chip: Next Generation Electronics”, IEE Press, ISBN: 0-86341-552-0.

Journal Articles

  1. A. Parihar, N. Shukla, S. Datta, and A. Raychowdhury, “Synchronization of pairwise-coupled, identical, relaxation oscillators based on metal-insulator phase transition devices: A Model Study” in Journal of Applied Physics, vol. 117, 054902 (2015)

  2. A. Parihar, N. Shukla, S. Datta, and A. Raychowdhury. Exploiting synchronization properties of correlated electron devices in a non-boolean computing fabric for template matching. IEEE Journal on Emerging and Selected Topics in Circuits and Systems,, PP(99):1–10, 2014.

  3. Abhinav Parihar, Nikhil Shukla, Suman Datta, and Arijit Raychowdhury. Synchronization of pairwise-coupled, identical, relaxation oscillators based on metal-insulator phase transition devices: A model study. arXiv preprint arXiv:1408.2582, 2014.

  4. Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, and Arijit Raychowdhury. A 32nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits. Journal of Solid State Circuits, 11, 2014.

  5. Nikhil Shukla, Parihar, Abhinav, Eugene Freeman, Hanjong Paik, Greg Stone, Vijaykrishnan Narayanan, Haidan Wen, Zhonghou Cai, Venkatraman Gopalan, Roman Engel-Herbert, et al. Synchronized charge oscillations in correlated electron systems. Nature Scientific reports, 4, 2014.

  6. Helia Naeimi, Charles Augustine, Arijit Raychowdhury, Shih-Lien Lu, and James Tschanz. Sttram scaling and retention failure. Intel Technology Journal, 17(1):54, 2013.

  7. A Raychowdhury, C. Tokunaga, W. Beltman, M. Deisher, J.W. Tschanz, and V. De. A 2.3 nJ/frame voice activity detector-based audio front-end for context-aware system-on- chip applications in 32-nm cmos. IEEE Journal of Solid-State Circuits, 48(8):1963–1969, Aug 2013.

  8. Arijit Raychowdhury, Bibiche Geuskens, Keith Bowman, James Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad Khellah, Vivek De, “Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays,” Journal of Solid State Circuits (JSSCC), Vol-46, Issue 4, April 2011

  9. C. Augustine, A. Raychowdhury, D. Somasekhar, K. Roy, V. De, “Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances,” Transactions on Electron Devices, Vol. 58, Issue 12, Dec 2011.

  10. Keith A Bowman, Carlos Tokunaga, James W Tschanz, Arijit Raychowdhury, Muhammad M Khellah, Bibiche M Geuskens, Shih-Lien Lu, Paolo A Aseron, Tanay Karnik, and Vivek K De. All-digital circuit-level dynamic variation monitor for silicon debug and adaptive clock control. Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(9):2017–2025, 2011

  11. 11.Keith A. Bowman, James W. Tschanz, Shih-Lien L. Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris B. Wilkerson, Tanay Karnik, and Vivek K. De, “A 45nm Resilient Microprocessor Core for Dynamic Variation Tolerance,” Journal of Solid State Circuits (JSSCC), Dec 2010

  12. 12.Sumeet Kumar Gupta, Arijit Raychowdhury and K. Roy, “Digital Computation in Sub-Threshold Region for Ultra-Low Power Operation: A Device-Circuit-System Co-Design Perspective,” Proceedings of IEEE, Vol. 98, Issue 2, 2010

  13. 13.Sumeet Kumar Gupta, Arijit Raychowdhury and K. Roy, “Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy” Journal of Applied Physics, Vol. 105, Issue 9, 2009.

  14. 14.Bowman, K.A.; Tokunaga, C.; Tschanz, J.W.; Raychowdhury, A.; Khellah, M.M.; Geuskens, B.M.; Lu, S.-L.L.; Aseron, P.A.; Karnik, T.; De, V.K.; , “All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control,” Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.58, no.9, pp.2017-2025, Sept. 2011

  15. 15.Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath, “A 1.05V 1.6mW, 0.45oC 3σ Resolution ΣΔ based Temperature Sensor with Parasitic Resistance Compensation in 32nm Digital CMOS Process,” Journal of Solid State Circuits (JSSCC), Vol 44, Issue 12, 2009, pp: 3621-3630.

  16. 16.Arijit Raychowdhury, Shekhar Borkar, Vivek De, Ali Keshavarzi and K. Roy, “Variation Tolerance in a Multi-channel Carbon Nanotube Transistor for High Speed Digital Circuits,” IEEE Transactions on Electron Devices (TED), Vol 56, Issue 3, March 2009, pp: 383-392.

  17. 17.A. Coker, V. Taylor, D. Bhaduri, S. Sukla, A. Raychowdhury, K. Roy, ”Multi-junction Fault Tolerance Architecture for Nanoscaled Crossbar memory,” IEEE Transactions on Nanotechnology (TNANO), Vol. 7, Issue 2, March 2008, pp: 202-208.

  18. 18.Arijit Raychowdhury, Bipul Paul, Swarup Bhunia, and Kaushik Roy, “Computing with Subthreshold Leakage: Device/Circuit/Architecture Co-design for Ultralow-Power Subthreshold Operation”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 13, Issue 11, November 2005, pp:  1213-1224.

  19. 19.Myeong-Eun Hwang, Arijit Raychowdhury, and Kaushik Roy, “Energy Recovery Techniques to Reduce On-chip Power Density in Molecular Nano-Technologies”, IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 52, no. 8, August 2005, pp:  1580-1589.

  20. 20.N. Banerjee, A. Raychowdhury, K. Roy, S. Bhunia, and H. Mahmoodi, “Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis” , IEEE Transactions on Very Large Scale Integration  Systems (TVLSI), Vol. 14, Issue 9, September 2006, pp: 1034-1039.

  21. 21.Arijit Raychowdhury, and Kaushik Roy, “Carbon Nanotube Electronics: Design of High Performance and Low Power Digital Circuits”, IEEE Transactions on Circuits and Systems I, Vol. 54, Issue 11, Nov 2007, pp 2391-2401.

  22. 22.Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Vivek De, and Kaushik Roy, “Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic – Modeling and DC Simulations”, IEEE Transactions on Electron Devices (TED), Vol. 53, Issue 11, November 2006, pp:  2711-2717.

  23. 23.Ali Keshavarzi, Arijit Raychowdhury, Juanita Kurtin, Kaushik Roy, and Vivek De, “Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic – Transient Analysis, Parasitics and Scalability”, IEEE Transactions on Electron Devices (TED), Vol. 53, Issue 11, November 2006, pp:  2718-2726.

  24. 24.Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, “A Novel Delay Fault Testing Methodology Using Low-Overhead Built-in Delay Sensor”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol 25, Issue 12, Dec 2006, pp: 2934-2943.

  25. 25.Arijit Raychowdhury and Kaushik Roy, “Modeling of Metallic Carbon Nanotube Interconnects for Circuit Simulations and a Comparison with Cu Interconnects for Scaled Technologies”, IEEE Transactions on Computer Aided Design (TCAD), Vol. 25, Issue 1, January 2006, pp:  58-65.

  26. 26.Arijit Raychowdhury and Kaushik Roy, “Carbon nanotube based voltage-mode multiple-valued logic design,” IEEE Transactions on Nanotechnology (TNANO), Vol. 4, Issue 2, March 2005, pp: 168 – 179.

  27. 27.Saibal Mukhopadhyay, Arijit Raychowdhury and Kaushik Roy, “Accurate Estimation of Total Leakage in Nanometer Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile,” IEEE Transactions on Computer Aided Design (TCAD), Vol. 24, Issue 3, March 2005, pp:  363- 381.

  28. 28.Arijit Raychowdhury, Saibal Mukhopadhyay and Kaushik Roy, “A Circuit Compatible Model of Ballistic Carbon Nanotube Field Effect Transistors”, IEEE Transactions on Computer Aided Design (TCAD), Vol. 23, no. 10, October 2004, pp: 1411-1420. (Most downloaded paper of 2004)

  29. 29.B. C. Paul, A. Raychowdhury, and K. Roy, “Device Optimization for Digital Subthreshold Operation,” IEEE Transactions on Electron Devices (TED), Vol. 52, Issue 2, February 2005 pp: 237- 247.

  30. 30.Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, “Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current,” Journal of Electronic Testing:  Theory and Applications, March, 2005.

  31. 31.Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current,” Journal of Electronic Testing:  Theory and Applications, Vol. 21, Issue 2, April 2005.

Refereed Conference Articles

  1. 1.Saad B. Nasir and A. Raychowdhury. On limit cycle oscillations of discrete time digital linear regulators. In Applied Power Electronics Conference, to appear, March 2015.

  2. 2.Saad B. Nasir andSamantak Gangopadhyay and A. Raychowdhury. A 130nm fully digital linear drop-out regulator with adaptive control and reduced dynamic stability for wide dynamic range of operation. In International Solid State Circuits Conference, to appear, Feb 2015.

  3. 3.N. Shukla, A. Parihar, M. Cotter, M. Barth, X. Li, N. Chandrammorthy, D. G. Schlom, V. Narayanan, A. Raychowdhury, and S. Datta. Pairwise coupled hybrid vanadium dioxide-mosfet (hvfet) oscillators for non-boolean associative computing. In IEEE International Electron Device Meeting, December 2014.

  4. 4.Suman Datta, Nikhil Shukla, Matthew Cotter, Parihar, Abhinav, and Arijit Raychowd- hury. Neuro inspired computing with coupled relaxation oscillators. In Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, pages 1–6. ACM, 2014.

  5. 5.Nasir, Saad Bin, Lee, Youngtak, and Arijit Raychowdhury. Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators. In 15th International Symposium on Quality Electronic Design (ISQED), pages 68–75. IEEE, 2014.

  6. 6.Gangopadhyay, Samantak, Lee, Youngtak, Nasir, Saad Bin, and Arijit Raychowdhury. Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, pages 1–6. IEEE, 2014.

  7. 7.C. Tokunaga, J.F. Ryan, C. Augustine, J.P. Kulkarni, Yi-Chun Shih, S.T. Kim, R. Jain, K. Bowman, A Raychowdhury, M.M. Khellah, J.W. Tschanz, and V. De. A graphics execution core in 22nm cmos featuring adaptive clocking, selective boosting and state- retentive sleep. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 108–109, Feb 2014.

  8. 8.Arijit Raychowdhury. Beyond charge based computation: Design space exploration of spin transfer torque based mrams for embedded applications. In IEEE International Symposium on Low Power Electronics and Design (ISLPED),, pages 135–138. IEEE, 2013.

  9. 9.Arijit Raychowdhury. Pulsed read in spin transfer torque (stt) memory bitcell for lower read disturb. In IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),, pages 34–35. IEEE, 2013.

  10. 10.Arijit Raychowdhury. Spin torque devices in embedded memory: model studies and design space exploration. In Proceedings of the International Conference on Computer- Aided Design, pages 572–575. IEEE Press, 2013.

  11. 11.Arijit Raychowdhury, Carlos Tokunaga, Willem Beltman, Michael Deisher, James Tschanz, Vivek De, “A 2.3nJ/Frame Voice Activity Detector for Context-Aware Systems in 32nm CMOS,” Proceedings of the Custom Integrated Circuit Conference (CICC), June 2012.

  12. 12.Rangharajan Venkatesan, Vivek Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy and Anand Raghunathan, “TapeCache: A High Density, Energy Efficient Cache Based on Domain Wall Memory,”, Proceedings of the International Symposium on Low Power Electronic Design, July, 2012 (Best Paper Award)

  13. 13.Arijit Raychowdhury, D. Somasekhar, J. Tschanz, V. De, “A fully-digital phase-locked low dropout regulator in 32nm CMOS,” Proceedings of the VLSI Circuit Symposium, June 2012.

  14. 14.James Tschanz, Keith Bowman, Shih-Lien Lu, Paolo Aseron, Muhammad Khellah, Arijit Raychowdhury, Bibiche Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De, “A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance,” Proceedings of the International Solid State Circuit Conference (ISSCC), 2010.

  15. 15.Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath, “A 1.05V 1.6mW, 0.45oC 3σ Resolution ΣΔ based Temperature Sensor with Parasitic Resistance Compensation in 32nm Digital CMOS Process,” Proceedings of the International Solid State Circuit Conference (ISSCC), 2009.

  16. 16.Nicolaidis, M.; Anghel, L.; Zergainoh, N.-E.; Zorian, Y.; Karnik, T.; Bowman, K.; Tschanz, J.; Shih-Lien Lu; Tokunaga, C.; Raychowdhury, A.; Khellah, M.; Kulkarni, J.; De, V.; Avresky, D.; , “Design for test and reliability in ultimate CMOS,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 , vol., no., pp.677-682, 12-16 March 2012

  17. 17.Arijit Raychowdhury, Bibiche Geuskens, Keith Bowman, James Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad Khellah, Vivek De, “Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM,” Proceedings of the VLSI Circuit Symposium, June 2010.

  18. 18.C. Augustine, A. Raychowdhury, D. Somasekhar, J. Tschanz, K. Roy, Vivek K. De, “Numerical Analysis of Typical STT-MTJ Stacks for 1T-1R Memory Arrays,” to be presented in the International Electron Devices Meeting (IEDM), Dec. 2010

  19. 19.Arijit Raychowdhury, Dinesh Somasekhar, Tanay Karnik, Vivek De, “Design Space and Scalability Exploration of 1T-1STT MTJ Memory Arrays in the Presence of Variability and Disturbances,” Digest of International Electron Device Meeting (IEDM), Dec. 2009.

  20. 20.Arijit Raychowdhury, Dinesh Somasekhar, Tanay Karnik, Vivek De, “Modeling and Analysis of Read (RD) Disturb in 1T-1STT MTJ Memory Bits”, Device Research Conference (DRC), 2010.

  21. 21.Arijit Raychowdhury, Bibiche Geuskens, Jaydeep Kulkarni, Jim Tschanz, Keith Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad Khellah, “PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction,” Proceedings of the International Solid State Circuit Conference (ISSCC), 2010.

  22. 22.Keith Bowman, James Tschanz,  Shih-Lien Lu, Paolo Aseron, Muhammad Khellah, Arijit Raychowdhury, Bibiche Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De, “Resilient Microprocessor Design for High Performance and Energy Efficiency,” Proceedings of the International Symposium on Low Power Electronics & Design (ISLPED), 2010, pp: 355-355.

  23. 23.James Tschanz, Keith Bowman, Muhammad Khellah, Chris Wilkerson, Bibiche Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De, “Resilient Design in Scaled CMOS for Energy Efficiency”, Proceedings of the ASP-DAC, 2010 (invited).

  24. 24.Jim Tschanz, Keith Bowman, Shih-Lien Lu, Paolo Aseron, Muhammad Khellah, Arijit Raychowdhury, Bibiche Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De, “On-Line Detection and Correction of Errors Due to Fast, Dynamic Voltage Droop Events,” IEEE Workshop on Silicon Errors in Logic – System Effects, Stanford University, 2010.

  25. 25.M-E. Hwang, Arijit Raychowdhury, Keejong Kim, and Kaushik Roy, “An 85mV 40nW Process-Tolerant Subthreshold 8X8 FIR Filter,” Proceedings of the VLSI Circuits Symposium, June 2007, pp: 154-155.

  26. 26.Arijit Raychowdhury, Xunyao Fong, Qikai Chen, and Kaushik Roy, “Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits”, Proc. of the International Symposium of Low Power Electronic Design (ISLPED), October 2006, pp: 1-6. (Best paper Award)

  27. 27.A. Raychowdhury, Jeong Il Kim, D. Peroulis, and K. Roy, “Integrated MEMS Switches for Leakage Control of Battery Operated Systems”, Proc. of the Custom Integrated Circuit Conference (CICC), September 2006.

  28. 28.A. Raychowdhury, Bipul Paul, Swarup Bhunia, and Kaushik Roy, “Ultralow Power Computing with Subthreshold Leakage: A Comparative Study of Bulk and SOI Technologies,” Proc. of the Design and Test in Europe (DATE), March 2006, pp: 1-6.

  29. 29.Bipul C Paul, Arijit Raychowdhury, and Kaushik Roy, “Device Optimization for Ultra-Low Power Digital Sub-Threshold Operation”, Proc. of the International Symposium on Low Power Electronics and Design (ISLPED), Newport Beach, USA, August 2004, pp: 96-101.

  30. 30.Arijit Raychowdhury and Kaushik Roy, “A Novel Multiple-Valued Logic Design Using Ballistic Carbon nanotube FETs”, Proc. of the 34th International Symposium on Multiple-Valued Logic (ISMVL), Toronto, May 2004, pp:  14-19.

  31. 31.A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A Feasibility Study of Subthreshold SRAM across Technology Generations”, Proc. Of International Conference on Computer Design (ICCD), San Jose, August 2005, pp: 417-422.

  32. 32.S. Mukhopadhay, A. Raychowdhury, K. Roy, H. Mahmoodi, “Leakage Current Based Stabilization Scheme for Robust Sense Amplifier Design for Yield Enhancement in Nanoscale SRAM,” Proceedings of Asian Test Symposium, 2005, pp: 176-181.

  33. 33.Arijit Raychowdhury, “Model study of 1T-1STT MTJ Memory Arrays for Embedded Applications,” Midwest Symposium on Circuits and Systems (MWCAS), Aug 2010. (invited)

  34. 34.Arijit Raychowdhury, Ali Keshavarzi, Vivek De, Shekhar Borkar, and Kaushik Roy, “The Theory of Multi-channel Carbon Nanotube Transistors for Variation Tolerant Digital Circuits,” Proc. Of the Device Research Conference (DRC), 2008.

  35. 35.Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark Lundstrom, Kaushik Roy, “PETE: A Device/Circuit Analysis Framework for Evaluation and Comparison Of Charge Based Emerging Devices,” Proceedings of ISQED, 2009. (Nominated for best paper award)

  36. 36.Arijit Raychowdhury, Charles Augustine, Yunfei Gao, Mark Lundstrom, and Kaushik Roy, “PETE: Purdue Emerging Technology Evaluator for estimating Power-Performance Trade-offs in Nanoscaled Circuits,” SRC TECHCON, 2008

  37. 37.Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Kaushik Roy, Vivek De “Scalability of Carbon Nanotube FET Circuits”, in the Proc. Of the Asian Solid State Circuits Conference (ASSCC), Nov. 2006, pp: 2-7.

  38. 38.Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Vivek De, and Kaushik Roy, “Optimal Spacing of Carbon Nanotubes in a CNFET Array for Highest Circuit Performance”, Proc. of the Device Research Conference (DRC), June 2006.

  39. 39.Mark Budnik, Arijit Raychowdhury, Aditya Bansal and Kaushik Roy, “CNCAP: Design of a high density Carbon Nanotube Capacitor Structure”, Proc. of the Design Automation Conference (DAC), July 2006.

  40. 40.Arijit Raychowdhury, and Kaushik Roy, “Using Super Cut-off Carbon Nanotube Sleep Transistors in Silicon Based Low Power Digital Circuits”, Proc. of the IEEE Nano, Cincinnati, June 2006.

  41. 41.Mark Budnik, Arijit Raychowdhury, Kaushik Roy, “Power Delivery for Nanoscale Processors with    Single Wall Carbon Nanotube Interconnects”, Proc. of the IEEE Nano, Cincinnati, June 2006.

  42. 42.A. Raychowdhury, and Kaushik Roy, “Carbon Nanotubes for Digital Circuit Design”, Proc. of the Government Microcircuit Applications and Critical Technology Conference, GomacTech, March 2005. (Invited)

  43. 43.Arijit Raychowdhury, Jing Guo, Kaushik Roy, and Mark Lundstrom, “Design of a novel three-valued static memory using Schottky barrier carbon nanotube FETs”, Proc. of the Fourth IEEE Nano Conference, Munich, July 2005, pp: 507 – 510.

  44. 44.Arijit Raychowdhury, Saibal Mukhopadhyay, and Kaushik Roy, “Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance”, Proc. of the Third IEEE-Nano Conference, San Francisco, August 2003, pp: 343-346. (Best Paper Award)

  45. 45.Arijit Raychowdhury and Kaushik Roy, “Carbon Nanotubes as Interconnects of the Future: A Circuit Perspective”, Proc. of the Advanced Metallization Conference, San Diego, October 2004. (Invited)

  46. 46.Arijit Raychowdhury and Kaushik Roy, “Circuit Modeling of Carbon Nanotube Interconnects and their Performance Estimation in VLSI Design”, Proc. of the International Workshop on Computational Electronics (IWCE), West Lafayette, October 2004.

  47. 47.Arijit Raychowdhury and Kaushik Roy, “A Circuit Model for Carbon Nanotube Interconnects: Comparative Study with Cu Interconnects for Scaled Technologies”, Proc. of the International Conference on Computer Aided Design (ICCAD), San Jose, November 2004, pp:  237-240.

  48. 48.Arijit Raychowdhury and Kaushik Roy, “Modeling and Analysis of Carbon Nanotube Interconnects for High Speed VLSI Design”, Proc. of the Fourth IEEE Nano Conference, Munich, August 2004, WE-P-37.

  49. 49.Arijit Raychowdhury, Jing Guo, Kaushik Roy, and Mark Lundstrom, “Choice of Flat-Band Voltage, VDD and Diameter of Ambipolar Schottky-Barrier Carbon Nanotube Transistors in Digital Circuit Design”, Proc. of the Fourth IEEE Nano Conference, Munich, August 2004, TH-2-2-1.

  50. 50.Arijit Raychowdhury, Saibal Mukhopadhyay, and Kaushik Roy, “Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation”, Proc. of the International Conference on Computer Aided Design (ICCAD), San Jose, November 2003, pp: 465-469.

  51. 51.Arijit Raychowdhury and Kaushik Roy, “Performance Estimation in Molecular Crossbar Architecture Considering Capacitive and Inductive Coupling Between Interconnects”, Proc. of the Third IEEE-Nano Conference, San Francisco, August 2003, pp: 445-448.

  52. 52.M. Cho, N. Sathe, A. Raychowdhury, S. Mukhopadhyay, “Optimization of Burn-in Test for Many-core Processors through Adaptive Spatiotemporal Power Migration,” to appear in the Proceedings of International Test Conference (ITC), Nov 2010.

  53. 53.Saibal Mukhopadhyay, Arijit Raychowdhury, and Kaushik Roy, “Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling”, Proc. of the Design Automation Conference (DAC), Anaheim, June 2003, pp. 169-174. (Nominated for best paper award)

  54. 54.A. Raychowdhury, S. Ghosh, K. Roy, “A Novel On-Chip Delay Measurement Hardware for Efficient Speed Binning,” Proceedings of the On-Line Testing Symposium, 2005, pp: 287-292.

  55. 55.A. Raychowdhury, S. Ghosh, S. Bhunia, K. Roy, “A Novel Delay Fault Testing Methodology using On-ship Low-overhead Delay Measurement Hardware at Strategic probe Points,” Proceedings of the European Testing Symposium, 2005, pp: 108-113.

  56. 56.S. Ghosh, S. Bhunia, A. Raychowdhury, K. Roy, “Delay fault localization in test-per-scan BIST using built-in delay sensor,” Proceedings of the On-Line Testing Symposium, 2006.

  57. 57.S. Bhunia, H. Mahmoodi, A. Raychowdhury, K. Roy, “First Level Hold: A Novel Low-overhead Delay Fault Testing Technique,” Proceedings of International Symposium on Defect and Fault Tolerance in VLSI Symstems, 2004.

Online Tools

  1. 1.“PETE: Purdue Emerging Technology Evaluator,” http://nanohub.org/tools/pete/ for estimating circuit level performance and power of novel devices. This has been used by researchers world-wide and has been used as the benchmarking tool in the Nanoelectronics Research Initiative (NRI) Program.

Patents: Issued and Pending

  1. 1.Arijit Raychowdhury, Charles Augustine, James Tschanz, Vivek De “A Digital Clamp for State Retention in Embedded Sequentials,” Filed with the USPTO, 2012.

  2. 2.Arijit Raychowdhury, James Tschanz, Vivek De, “Spin Transfer Torque Based Memory Elements for Programmable Device Arrays,” PCT/US2012/031371, 2012

  3. 3.Arijit Raychowdhury, Dinesh Somasekhar, James Tschanz, Vivek De, “Digitally Phase Locked Low Drop-out Regulator,” PCT/US2012/057066, 2012.

  4. 4.Arijit Raychowdhury, B. Doyle, David Kencke, Charles Kuo, James Tschanz, Fatih Hamazaoglu, Eric Wang, R. Golizadeh, “Methods and Systems to Read a Magnetic Tunnel Junction Based Memory Cell Based on a Pulsed Read Current,” PCT/US2012/030490, 2012.

  5. 5.Marco Beltman, Matias Zanartu, Arijit Raychowdhury, Anand Rangarajan, Michael Deisher, “Speech Audio Processing,” US 10-2012-7031843, 2011.

  6. 6.Marco Beltman, Matias Zanartu, Arijit Raychowdhury, Anand Rangarajan, Michael Deisher, “Speech Audio Processing,” PCT/US2011/042515, 2011.

  7. 7.Charles Kuo, B. Doyle, Arijit Raychowdhury, R. Golizadeh, Oguz Kaan, “Balancing Energy Barrier Between States in Perpendicular Magnetic Tunnel Junctions,” PCT/US2011/068158, 2011.

  8. 8.Brian Doyle, Arijit Raychowdhury, Yong Ju, Charles Kuo, Oguz Kaan, David Kencke, R. Chau, R. Golizadeh, “Memory with Elements Having Two Stacked Magentic Tunneling Junctions Devices,” PCT/US2011/066979, 2011.

  9. 9.Arijit Raychowdhury, J. Kulkarni, James Tschanz, “Multi-Supply Sequential Logic Unit,” PCT/US2011/064848, 2011.

  10. 10.Dia Khalil, Arijit Raychowdhury, Muhammad Khellah, Ali Keshavarzi, “Leakage Compoensation Circuit for Dynamic Random Access Memory Cells,” US 7,961,498, 2008.

  11. 11.Jaydeep Kulkarni, M. Khellah, B. Gueskens, Arijit Raychowdhury, T. Karnik, V. De, “Memory Write Operation Methods and Circuits,” US 12/823,642, 2010.

  12. 12.Arijit Raychowdhury, J. Kulkarni, James Tschanz, “Multi-Supply Sequential Logic Unit,” US 101143110, 2010.

  13. 13.Jaydeep Kulkarni, M. Khellah, B. Gueskens, Arijit Raychowdhury, T. Karnik, V. De, “Memory Write Operation Methods and Circuits,” PCT/US2011/040458, 2011.

  14. 14.H. Lakhdawala, William Li, Gregory Taylor, Krishnamurthy Soumyanath, Arijit Raychowdhury, “Thermal Sensor Device,” 8,096,707, 2008.

  15. 15.Arijit Raychowdhury, Marco Beltman, James Tschanz, Carlos Tokunaga, Mike Deisher, Tomas Walsh, “Low Power Voice Detection,” PCT/US2011/063622, 2011.

  16. 16.Muhammad Khellah, B. Gueskens, Arijit Raychowdhury, “Method and System to Lower the Minimum Operating Voltage of a Memory Array,” US 8,094,505, 2009.

  17. 17.Sandeep Oswal, Arijit Raychowdhury, Prakash E., Fernando Mujica, “Adaptive Cancellation Network System And Method For Digital Subscriber Line”, US Patent no. 7298838, 2007.

  18. 18.Arijit Raychowdhury, Ali Keshavarzi, J. Kurtin, Vivek De, “Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby,” US 11/648,209, 2006.

  19. 19.Sandeep Oswal, Arijit Raychowdhury, Prakash E., Fernando Mujica, “DSL modem and method for reducing transmit echo therein,” European Patent EP1333591, 2006.

  20. 20.Mark Budnik, Arijit Raychowdhury, Aditya Bansal and Kaushik Roy, “High Density Capacitors for Integrated Circuit Technologies”, US Patent no. 20070171594, 2009.

Theses and Dissertations

Arijit Raychowdhury, “Carbon Nanotube Electronics: Device Models and Applications in VLSI Circuits”, PhD. Thesis, Purdue University (Awarded: Dmitri N. Chorafas Award and the Best Thesis Award, 2007).

Invited Talks and Tutorials

  1. 1.Adaptive Designs in Computation and Power Management, International Conference on Computer Aided Design (ICCAD), San Jose, Nov. 2014

  2. 2.Voltage Regulators for Wide Dynamic Range, IBM T. J. Watson Research Lab, NY, Oct. 2014

  3. 3.On Die Digital Voltage Regulators with Continuous Time and Discrete Time Control for Loads with Wide Dynamic Range of Operation, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), Austin, May 2014

  4. 4.Linear Regulation: The Role of Adaptive Control, Intel Corporation, Hillsboro, OR, Nov. 2013

  5. 5.Computing with Spin: Beyond Charge Based Electronics, International Conference on Computer Aided Design (ICCAD), Nov. 2013

  6. 6.Adaptive and Resilient Circuits for Improving Energy Efficiency in Wide Dynamic Range Digital Systems, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Monterey Bay, USA, Oct. 2013

  7. 7.Spintronics for Embedded Memory: A Model Study, International Symposium on Low Power Electronic Design(ISLPED), Oct. 2013

  8. 8.High-Efficiency On-Die Digital Linear Voltage Regulators with On-Line Adaptation for Loads with Wide Dynamic Range of Operation,Qualcomm Inc., Raleigh, USA, Oct. 2013

  9. 9.Adaptive SRAM Circuits, Design and Test in Europe (DATE), Grenoble, France, Mar. 2013

  10. 10.Spintronics for Embedded Non-volatile Electronics, International Electron Device Meet- ing (IEDM), San Francisco, USA, Dec. 2012

  11. 11.1T-1STT MTJ Based Embedded Memory Arrays, Spintronics Workshop on LSI, Hawaii, USA, Jun. 2012.

  12. 12.1T-1STT MTJ Memory Arrays for Embedded Applications, Non-volatile Memory Workshop, San Diego, USA, March 2011

  13. 13.Design Considerations for 1T-1STT MTJ Based Embedded Memory Arrays, CSIS International Symposium on Spintronics Based VLSI, Sendai, Japan, Feb. 2011

  14. 14.Designing Adaptive and Resilient Digital Systems, Invited Speaker Series, University of Washington, Seattle, Washington, Oct. 2010

  15. 15.Carbon Nanotube Electronics: Modeling, Circuit Implications, and Challenges, Univer- sity of Michigan, Ann Arbor, Mar. 2007

  16. 16.Subthreshold Design: Prospects and Challenges, University of Waterloo, Waterloo, Canada, Apr. 2007

  17. 17.Designing with Subthreshold logic: From Devices to Systems, University of Florida, Florida, Mar. 2007

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